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= '''RISC-V''' =
 
== Overview ==
[[Sisyphus]] port for riscv64 (RV64GC) architecture is under development since early 2018. The following platforms are supported:
 
* [[HiFive Unmatched]]
* [[HiFive Unleashed]]
* [[Ports/riscv64/QEMU|QEMU]]
 
== RISC-V ==


RISC-V is an [https://riscv.org/risc-v-isa open and free instruction set architecture (ISA)].
RISC-V is an [https://riscv.org/risc-v-isa open and free instruction set architecture (ISA)].
The RISC-V ISA specifications are licensed under a [https://creativecommons.org/licenses/by/4.0/ Creative Commons license (CC BY 4.0)].
The RISC-V ISA specifications are licensed under a [https://creativecommons.org/licenses/by/4.0/ Creative Commons license (CC BY 4.0)].
Anyone could get the final versions of the [https://riscv.org/specifications/ user-level ISA specifications] and drafts
Anyone could get the final versions of the [https://riscv.org/specifications/ ISA specifications] and participate in their development.
of the [https://riscv.org/specifications/compressed-isa/ compressed] and [https://riscv.org/specifications/privileged-isa/ privileged] ISA specifications.
 
Another key feature of the RISC-V architecture that it is scalable and allows multiple implementations. The minimal specification has commands to store, load, jump and integer arithmetic.  It supports the 32-, 64- and 128-bit register sizes: "RV32I, RV64I and RV128I" ("I" stands for integer). Implementations can provide additional functionality by extending the basic ISA -- that is, implementing standard or vendor-specific extensions.
 
This Linux port runs on "RV64IMAFDC"<ref>In 2019, RISC-V ISA specification extracted two new extensions, Zifencei and  Zicsr, from the mandatory base instruction set, and added them to 'G' set. But I'd like to constrain myself from elaborating on this in what should be a short introductory section.</ref> architecture, which means RV64I with the following standard extensions:
* <tt>'''M'''</tt> - Multiply and divide;
* <tt>'''A'''</tt> - Atomic operations;
* <tt>'''F'''</tt> - Single precision floating point;
* <tt>'''D'''</tt> - Double precision floating point;
* <tt>'''C'''</tt> - Compressed instructions.
 
For convenience, this architecture is abbreviated as "RV64GC" ("G" == "IMAFD").


Another key feature of the RISC-V architecture that it is scalable and allows multiple implementations. The minimal specification has the
== Images ==
commands to store and load, jump and integer arithmetic. It supports the 32-, 64- and 128-bit register sizes: "RV32I, RV64I and RV128I" ("I" stands for integer).
This Linux port runs on "RV64IMAFDC" or "RV64GC" ("G" == "IMAFD"):
* <tt>'''I'''</tt> - Integer and basic instructions
* <tt>'''M'''</tt> - Multiply and divide
* <tt>'''A'''</tt> - Atomic operations
* <tt>'''F'''</tt> - Single precision floating point
* <tt>'''D'''</tt> - Double precision floating point
* <tt>'''C'''</tt> - Compressed instructions


At this page one could find the latest information about ALT port status for the new platform - RISC-V (RV64GC). We're building it on the [https://www.crowdsupply.com/sifive/hifive-unleashed HiFive Unleashed] board from SiFive.
We build [[Regular/riscv64|Regular Images]] (see also: [[Regular]]) for the supported boards and QEMU. Check out [[Regular/riscv64]] for download links and the platform page for the quick start/installation instructions.
If you want to test the ALT port (''QEMU or HiFive Unleashed'') or take part in the development please refer to [https://en.altlinux.org/Regular/riscv64 this page].
== '''Working plan''' ==


* The following Linux kernels have been bare metal tested on SiFive HiFive Unleashed:
Also, for Unmatched/Unleashed and QEMU, [[Simply Linux 10]] was released.
** 4.15
** 4.19-rc2
** 4.19.6 ([http://git.altlinux.org/people/arei/packages/kernel-image.git?p=kernel-image.git;a=commit;h=a420ee4217797b60b27ce60fd80a39166ddf2143 git])
** 5.0.19 ([http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/riscv64/RPMS.classic/kernel-image-un-def-5.0.19-alt2.rv64gc.riscv64.rpm image RPM],[http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/files/SRPMS/kernel-image-un-def-5.0.19-alt2.rv64gc.src.rpm SRPM], [http://git.altlinux.org/people/arei/packages/kernel-image-un-def.git?p=kernel-image-un-def.git;a=summary git])
** (experimetnal) 5.1.9 ([http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/riscv64/RPMS.classic/kernel-experimental-5.1.9-alt1.riscv64.rpm image RPM], [http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/files/SRPMS/kernel-experimental-5.1.9-alt1.src.rpm SRPM], [http://git.altlinux.org/people/arei/packages/kernel-experimental.git?p=kernel-experimental.git;a=summary git])


* BOOT methods:
== Repository ==
** Berkeley bootloader -- '''DONE'''
** U-BOOT ([http://git.altlinux.org/people/lineprinter/public/u-boot.git?p=u-boot.git;a=blob;f=README.alt;hb=HEAD link]) -- '''DONE'''


* [[Sisyphus]] port -- '''IN PROGRESS'''
RPM/SRPM repository is located at http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/  
*# Toolchain -- '''DONE'''
*# Linux Kernel -- '''DONE'''
*# X11 -- '''DONE'''
*# Desktop Environments -- '''IN PROGRESS'''
* ALT image ([http://en.altlinux.org/Regular/riscv64 link]) -- '''DONE'''
* [http://git.altlinux.org/people/arei/packages/girar.git?p=girar.git;a=shortlog;h=refs/heads/riscvmod Girar Builder] -- '''DONE'''
* QEMU image ([[#QEMU|see below]]) -- '''DONE'''


The RPM/SRPM repository at [http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/ here].
As apt-rpm <tt>sources.list</tt>:


== '''OpenOCD''' ==
rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 classic
# rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 debuginfo
rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/noarch  classic


The OpenOCD ([http://openocd.org/documentation/ docs]) is a tool for debugging, in-system programming and boundary-scan testing for embedded target devices. It is particularly useful for low-level debugging with ([https://www.gnu.org/software/gdb/ GDB]) of the bootloader, Linux kernel, etc.
Yandex mirror (better download speeds):


To debug HiFive Unleashed with OpenOCD the following steps are needed:
rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 classic
# rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 debuginfo
rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/noarch  classic


# Connect HiFive Unleashed and PC with USB and power it on. This interface provides UART0 (/dev/ttyUSB1) and JTAG interfaces by FTDI FT2232H ([https://www.ftdichip.com/Products/ICs/FT2232H.html link]).
The information on the available packages is available here: https://packages.altlinux.org/en/sisyphus_riscv64/packages/
# Run (see simple config below and do not forget to add user to the plugdev group): <source lang=shell>$ openocd -s <path to the directory with hifive-u.cfg> -f hifive-u.cfg</source>OpenOCD will listen port 3333 for GDB connection.
# Run GDB compiled with riscv64 target support.
# Attach GDB to the OpenOCD: <source lang=shell>gdb$ target extended-remote localhost:3333</source>
# Now one could set breakpoints, investigate memory, disassemble memory regions, etc. It is possible to load an ELF file with debug information to import symbols and place breakpoints to symbols.


Example of the simple hifive-u.cfg:
The packages are build on a separate [[girar]] instance, similar to [[Git.alt]]. SiFive [[HiFive Unmatched]] are used as build nodes.


<source lang="shell>
The "chasing builder" approach is used: as soon as a task is committed to the primary [[Sisyphus]] repository, special robot creates a similar task for <tt>sisyphus_riscv64</tt>. This means that there is no need to do anything special for building packages for '''riscv64''': build for Sisyphus. The tasks are approved manually. The resulting packages are available in the repository on the same day or on the next day most of the times.
adapter_khz 1000


interface ftdi
We don't rebuild all the Sisyphus packages due to the limited need and resources. If you need some package that is available in Sisyphus but is missing in <tt>sisyphus_riscv64</tt>, please fill a bug or write to the mailing list: riscv-devel@lists.altlinux.org.
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010


ftdi_channel 0
== Reporting issues ==
ftdi_layout_init 0x0018 0x001b


set _CHIPNAME riscv
For tracking bugs and issues we use ALT Linux Team bugzilla -- http://bugzilla.altlinux.org (see also: [[BugTracking]]).
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913


set _TARGETNAME $_CHIPNAME.cpu
* For issues in packages, choose product: Sisyphus, component: name of the package, and set "hardware" field to '''riscv64'''.
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
* For general image issues, choose product corresponding to the image type (e.g. Regular, or Simply Linux).
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1


init
'''IMPORTANT''':
halt
* Set '''Hardware''' to '''riscv64''' (on the right at the top of the bug creation form)
echo "Ready for Remote Connections"
* Assign the bug to Ivan Melnikov (iv at altlinux.org).
</source>


== '''Useful links''' ==
== Useful links ==


* [[Ports/riscv64/OpenOCD]]
* [http://0x1.tv/20180929H OSSDEVCONF-2018 (in Russian)]
* [https://github.com/dalegr/riscv-bbl-utils Berkeley bootloader utils] to merge the linux kernel into the bbl.bin with dummy payload.
* [https://github.com/dalegr/riscv-bbl-utils Berkeley bootloader utils] to merge the linux kernel into the bbl.bin with dummy payload.
* [https://riscv.org/specifications RISC-V specifications]
* [https://riscv.org/specifications RISC-V specifications]
* [https://www.sifive.com/blog/all-aboard-part-0-introduction All Aboard] -- cool series of blog posts by Palmer Dabbelt about RISC-V, toolchain, etc.
* [https://www.sifive.com/blog/all-aboard-part-0-introduction All Aboard] -- cool series of blog posts by Palmer Dabbelt about RISC-V, toolchain, etc.
* [http://0x1.tv/20180929H OSSDEVCONF-2018 (in Russian)]


[[Category:Sisyphus]]
[[Category:Sisyphus]][[Category:Ports]][[Category:RISC-V]]
[[ru:Ports/riscv64]]
[[ru:Ports/riscv64]]
{{Category navigation|title=Ports|category=Ports|sortkey=*}}

Latest revision as of 12:41, 18 November 2022

Overview

Sisyphus port for riscv64 (RV64GC) architecture is under development since early 2018. The following platforms are supported:

RISC-V

RISC-V is an open and free instruction set architecture (ISA). The RISC-V ISA specifications are licensed under a Creative Commons license (CC BY 4.0). Anyone could get the final versions of the ISA specifications and participate in their development.

Another key feature of the RISC-V architecture that it is scalable and allows multiple implementations. The minimal specification has commands to store, load, jump and integer arithmetic. It supports the 32-, 64- and 128-bit register sizes: "RV32I, RV64I and RV128I" ("I" stands for integer). Implementations can provide additional functionality by extending the basic ISA -- that is, implementing standard or vendor-specific extensions.

This Linux port runs on "RV64IMAFDC"[1] architecture, which means RV64I with the following standard extensions:

  • M - Multiply and divide;
  • A - Atomic operations;
  • F - Single precision floating point;
  • D - Double precision floating point;
  • C - Compressed instructions.

For convenience, this architecture is abbreviated as "RV64GC" ("G" == "IMAFD").

Images

We build Regular Images (see also: Regular) for the supported boards and QEMU. Check out Regular/riscv64 for download links and the platform page for the quick start/installation instructions.

Also, for Unmatched/Unleashed and QEMU, Simply Linux 10 was released.

Repository

RPM/SRPM repository is located at http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/

As apt-rpm sources.list:

rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 classic
# rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 debuginfo 
rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/noarch  classic

Yandex mirror (better download speeds):

rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 classic 
# rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 debuginfo
rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/noarch  classic

The information on the available packages is available here: https://packages.altlinux.org/en/sisyphus_riscv64/packages/

The packages are build on a separate girar instance, similar to Git.alt. SiFive HiFive Unmatched are used as build nodes.

The "chasing builder" approach is used: as soon as a task is committed to the primary Sisyphus repository, special robot creates a similar task for sisyphus_riscv64. This means that there is no need to do anything special for building packages for riscv64: build for Sisyphus. The tasks are approved manually. The resulting packages are available in the repository on the same day or on the next day most of the times.

We don't rebuild all the Sisyphus packages due to the limited need and resources. If you need some package that is available in Sisyphus but is missing in sisyphus_riscv64, please fill a bug or write to the mailing list: riscv-devel@lists.altlinux.org.

Reporting issues

For tracking bugs and issues we use ALT Linux Team bugzilla -- http://bugzilla.altlinux.org (see also: BugTracking).

  • For issues in packages, choose product: Sisyphus, component: name of the package, and set "hardware" field to riscv64.
  • For general image issues, choose product corresponding to the image type (e.g. Regular, or Simply Linux).

IMPORTANT:

  • Set Hardware to riscv64 (on the right at the top of the bug creation form)
  • Assign the bug to Ivan Melnikov (iv at altlinux.org).

Useful links

  1. In 2019, RISC-V ISA specification extracted two new extensions, Zifencei and Zicsr, from the mandatory base instruction set, and added them to 'G' set. But I'd like to constrain myself from elaborating on this in what should be a short introductory section.