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== Overview == | |||
[[Sisyphus]] port for riscv64 (RV64GC) architecture is under development since early 2018. The following platforms are supported: | |||
* [[HiFive Unmatched]] | |||
* [[HiFive Unleashed]] | |||
* [[Ports/riscv64/QEMU|QEMU]] | |||
== RISC-V == | |||
RISC-V is an [https://riscv.org/risc-v-isa open and free instruction set architecture (ISA)]. | RISC-V is an [https://riscv.org/risc-v-isa open and free instruction set architecture (ISA)]. | ||
The RISC-V ISA specifications are licensed under a [https://creativecommons.org/licenses/by/4.0/ Creative Commons license (CC BY 4.0)]. | The RISC-V ISA specifications are licensed under a [https://creativecommons.org/licenses/by/4.0/ Creative Commons license (CC BY 4.0)]. | ||
Anyone could get the final versions of the [https://riscv.org/specifications/ | Anyone could get the final versions of the [https://riscv.org/specifications/ ISA specifications] and participate in their development. | ||
of the | |||
Another key feature of the RISC-V architecture that it is scalable and allows multiple implementations. The minimal specification has commands to store, load, jump and integer arithmetic. It supports the 32-, 64- and 128-bit register sizes: "RV32I, RV64I and RV128I" ("I" stands for integer). Implementations can provide additional functionality by extending the basic ISA -- that is, implementing standard or vendor-specific extensions. | |||
This Linux port runs on "RV64IMAFDC"<ref>In 2019, RISC-V ISA specification extracted two new extensions, Zifencei and Zicsr, from the mandatory base instruction set, and added them to 'G' set. But I'd like to constrain myself from elaborating on this in what should be a short introductory section.</ref> architecture, which means RV64I with the following standard extensions: | |||
* <tt>'''M'''</tt> - Multiply and divide; | |||
* <tt>'''A'''</tt> - Atomic operations; | |||
* <tt>'''F'''</tt> - Single precision floating point; | |||
* <tt>'''D'''</tt> - Double precision floating point; | |||
* <tt>'''C'''</tt> - Compressed instructions. | |||
For convenience, this architecture is abbreviated as "RV64GC" ("G" == "IMAFD"). | |||
== Images == | |||
We build [[Regular/riscv64|Regular Images]] (see also: [[Regular]]) for the supported boards and QEMU. Check out [[Regular/riscv64]] for download links and the platform page for the quick start/installation instructions. | |||
Also, for Unmatched/Unleashed and QEMU, [[Simply Linux 10]] was released. | |||
== Repository == | |||
RPM/SRPM repository is located at http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/ | |||
As apt-rpm <tt>sources.list</tt>: | |||
rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 classic | |||
# rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 debuginfo | |||
rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/noarch classic | |||
Yandex mirror (better download speeds): | |||
rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 classic | |||
# rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 debuginfo | |||
rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/noarch classic | |||
The information on the available packages is available here: https://packages.altlinux.org/en/sisyphus_riscv64/packages/ | |||
The packages are build on a separate [[girar]] instance, similar to [[Git.alt]]. SiFive [[HiFive Unmatched]] are used as build nodes. | |||
The port is using "follower girar" (aka "chasing build") approach: as soon as a task is committed into [[Sisyphus]] repository, a special robot creates the similar task for sisyphus_riscv64; the tasks are then approved by the port maintainers. Usually, the packages are available in the repository on the same day the package was build for the primary Sisyphus, or on the next day. | |||
This means that there is no need to do anything special for building packages for '''riscv64''': build for Sisyphus. | |||
We don't rebuild all the Sisyphus packages due to the limited need and resources. If you need some package that is available in Sisyphus but is missing in <tt>sisyphus_riscv64</tt>, please fill a bug or write to the mailing list: riscv-devel@lists.altlinux.org. | |||
== Reporting issues == | |||
For tracking bugs and issues we use ALT Linux Team bugzilla -- http://bugzilla.altlinux.org (see also: [[BugTracking]]). | |||
* For issues in packages, choose product: Sisyphus, component: name of the package, and set "hardware" field to '''riscv64'''. | |||
* For general image issues, choose product corresponding to the image type (e.g. Regular, or Simply Linux). | |||
'''IMPORTANT''': | |||
* Set '''Hardware''' to '''riscv64''' (on the right at the top of the bug creation form) | |||
* Assign the bug to Ivan Melnikov (iv at altlinux.org). | |||
== Useful links == | |||
* [[Ports/riscv64/OpenOCD]] | |||
* [http://0x1.tv/20180929H OSSDEVCONF-2018 (in Russian)] | |||
* [https://github.com/dalegr/riscv-bbl-utils Berkeley bootloader utils] to merge the linux kernel into the bbl.bin with dummy payload. | * [https://github.com/dalegr/riscv-bbl-utils Berkeley bootloader utils] to merge the linux kernel into the bbl.bin with dummy payload. | ||
* [https://riscv.org/specifications RISC-V specifications] | * [https://riscv.org/specifications RISC-V specifications] | ||
* [https://www.sifive.com/blog/all-aboard-part-0-introduction All Aboard] -- cool series of blog posts by Palmer Dabbelt about RISC-V, toolchain, etc. | * [https://www.sifive.com/blog/all-aboard-part-0-introduction All Aboard] -- cool series of blog posts by Palmer Dabbelt about RISC-V, toolchain, etc. | ||
[[ | [[Category:Sisyphus]][[Category:Ports]][[Category:RISC-V]] | ||
[[ru:Ports/riscv64]] | |||
Latest revision as of 10:43, 20 November 2023
Overview
Sisyphus port for riscv64 (RV64GC) architecture is under development since early 2018. The following platforms are supported:
RISC-V
RISC-V is an open and free instruction set architecture (ISA). The RISC-V ISA specifications are licensed under a Creative Commons license (CC BY 4.0). Anyone could get the final versions of the ISA specifications and participate in their development.
Another key feature of the RISC-V architecture that it is scalable and allows multiple implementations. The minimal specification has commands to store, load, jump and integer arithmetic. It supports the 32-, 64- and 128-bit register sizes: "RV32I, RV64I and RV128I" ("I" stands for integer). Implementations can provide additional functionality by extending the basic ISA -- that is, implementing standard or vendor-specific extensions.
This Linux port runs on "RV64IMAFDC"[1] architecture, which means RV64I with the following standard extensions:
- M - Multiply and divide;
- A - Atomic operations;
- F - Single precision floating point;
- D - Double precision floating point;
- C - Compressed instructions.
For convenience, this architecture is abbreviated as "RV64GC" ("G" == "IMAFD").
Images
We build Regular Images (see also: Regular) for the supported boards and QEMU. Check out Regular/riscv64 for download links and the platform page for the quick start/installation instructions.
Also, for Unmatched/Unleashed and QEMU, Simply Linux 10 was released.
Repository
RPM/SRPM repository is located at http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/
As apt-rpm sources.list:
rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 classic # rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 debuginfo rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/noarch classic
Yandex mirror (better download speeds):
rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 classic # rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 debuginfo rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/noarch classic
The information on the available packages is available here: https://packages.altlinux.org/en/sisyphus_riscv64/packages/
The packages are build on a separate girar instance, similar to Git.alt. SiFive HiFive Unmatched are used as build nodes.
The port is using "follower girar" (aka "chasing build") approach: as soon as a task is committed into Sisyphus repository, a special robot creates the similar task for sisyphus_riscv64; the tasks are then approved by the port maintainers. Usually, the packages are available in the repository on the same day the package was build for the primary Sisyphus, or on the next day.
This means that there is no need to do anything special for building packages for riscv64: build for Sisyphus.
We don't rebuild all the Sisyphus packages due to the limited need and resources. If you need some package that is available in Sisyphus but is missing in sisyphus_riscv64, please fill a bug or write to the mailing list: riscv-devel@lists.altlinux.org.
Reporting issues
For tracking bugs and issues we use ALT Linux Team bugzilla -- http://bugzilla.altlinux.org (see also: BugTracking).
- For issues in packages, choose product: Sisyphus, component: name of the package, and set "hardware" field to riscv64.
- For general image issues, choose product corresponding to the image type (e.g. Regular, or Simply Linux).
IMPORTANT:
- Set Hardware to riscv64 (on the right at the top of the bug creation form)
- Assign the bug to Ivan Melnikov (iv at altlinux.org).
Useful links
- Ports/riscv64/OpenOCD
- OSSDEVCONF-2018 (in Russian)
- Berkeley bootloader utils to merge the linux kernel into the bbl.bin with dummy payload.
- RISC-V specifications
- All Aboard -- cool series of blog posts by Palmer Dabbelt about RISC-V, toolchain, etc.
- ↑ In 2019, RISC-V ISA specification extracted two new extensions, Zifencei and Zicsr, from the mandatory base instruction set, and added them to 'G' set. But I'd like to constrain myself from elaborating on this in what should be a short introductory section.