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= '''RISC-V''' =


RISC-V is an [https://riscv.org/risc-v-isa open and free instruction set architecture (ISA)].
== Overview ==
The RISC-V ISA specifications are licensed under a [https://creativecommons.org/licenses/by/4.0/ Creative Commons license (CC BY 4.0)].
[[Sisyphus]] port for riscv64 (RV64GC) architecture is under development since early 2018. The following platforms are supported:
Anyone could get the final versions of the [https://riscv.org/specifications/ user-level ISA specifications] and drafts
of the [https://riscv.org/specifications/compressed-isa/ compressed] and [https://riscv.org/specifications/privileged-isa/ privileged] ISA specifications.


Another key feature of the RISC-V architecture that it is scalable and allows multiple implementations. The minimal specification has the
* [[HiFive Unmatched]]
commands to store and load, jump and integer arithmetic. It supports the 32-, 64- and 128-bit register sizes: "RV32I, RV64I and RV128I" ("I" stands for integer).
* [[HiFive Unleashed]]
This Linux port runs on "RV64IMAFDC" or "RV64GC" ("G" == "IMAFD"):
* [[Ports/riscv64/QEMU|QEMU]]
* <tt>'''I'''</tt> - Integer and basic instructions
* <tt>'''M'''</tt> - Multiply and divide
* <tt>'''A'''</tt> - Atomic operations
* <tt>'''F'''</tt> - Single precision floating point
* <tt>'''D'''</tt> - Double precision floating point
* <tt>'''C'''</tt> - Compressed instructions


At this page one could find the latest information about ALT port status for the new platform - RISC-V (RV64GC). We're building it on the [https://www.crowdsupply.com/sifive/hifive-unleashed HiFive Unleashed] board from SiFive.
== RISC-V ==
If you want to test the ALT port (''QEMU or HiFive Unleashed'') or take part in the development please refer to [https://en.altlinux.org/Regular/riscv64 this page].
== '''Working plan''' ==


* The following Linux kernels have been bare metal tested on SiFive HiFive Unleashed:
RISC-V is an [https://riscv.org/risc-v-isa open and free instruction set architecture (ISA)].
** 4.15, 4.19-rc2, 4.19.6, 5.0.19, 5.1.9
The RISC-V ISA specifications are licensed under a [https://creativecommons.org/licenses/by/4.0/ Creative Commons license (CC BY 4.0)].
** Current: 5.9.1 [http://git.altlinux.org/people/arei/packages/kernel-image-un-def.git?p=kernel-image-un-def.git;a=shortlog;h=refs/heads/sisyphus_riscv64 git]
Anyone could get the final versions of the [https://riscv.org/specifications/ ISA specifications] and participate in their development.


* BOOT methods:
Another key feature of the RISC-V architecture that it is scalable and allows multiple implementations. The minimal specification has commands to store, load, jump and integer arithmetic.  It supports the 32-, 64- and 128-bit register sizes: "RV32I, RV64I and RV128I" ("I" stands for integer). Implementations can provide additional functionality by extending the basic ISA -- that is, implementing standard or vendor-specific extensions.
** Berkeley bootloader -- '''DONE'''
** U-BOOT ([http://git.altlinux.org/people/lineprinter/public/u-boot.git?p=u-boot.git;a=blob;f=README.alt;hb=HEAD link]) -- '''DONE'''


* [[Sisyphus]] port -- '''IN PROGRESS'''
This Linux port runs on "RV64IMAFDC"<ref>In 2019, RISC-V ISA specification extracted two new extensions, Zifencei and  Zicsr, from the mandatory base instruction set, and added them to 'G' set. But I'd like to constrain myself from elaborating on this in what should be a short introductory section.</ref> architecture, which means RV64I with the following standard extensions:
*# Toolchain -- '''DONE'''
* <tt>'''M'''</tt> - Multiply and divide;
*# Linux Kernel -- '''DONE'''
* <tt>'''A'''</tt> - Atomic operations;
*# X11 -- '''DONE'''
* <tt>'''F'''</tt> - Single precision floating point;
*# Desktop Environments -- '''IN PROGRESS'''
* <tt>'''D'''</tt> - Double precision floating point;
* ALT image ([http://en.altlinux.org/Regular/riscv64 link]) -- '''DONE'''
* <tt>'''C'''</tt> - Compressed instructions.
* [http://git.altlinux.org/people/arei/packages/girar.git?p=girar.git;a=shortlog;h=refs/heads/riscvmod Girar Builder] -- '''DONE'''
* QEMU image ([[#QEMU|see below]]) -- '''DONE'''


The RPM/SRPM repository at [http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/ here].
For convenience, this architecture is abbreviated as "RV64GC" ("G" == "IMAFD").


== '''OpenOCD''' ==
== Images ==


The OpenOCD ([http://openocd.org/documentation/ docs]) is a tool for debugging, in-system programming and boundary-scan testing for embedded target devices. It is particularly useful for low-level debugging with ([https://www.gnu.org/software/gdb/ GDB]) of the bootloader, Linux kernel, etc.
We build [[Regular/riscv64|Regular Images]] (see also: [[Regular]]) for the supported boards and QEMU. Check out [[Regular/riscv64]] for download links and the platform page for the quick start/installation instructions.


To debug HiFive Unleashed with OpenOCD the following steps are needed:
Also, for Unmatched/Unleashed and QEMU, [[Simply Linux 10]] was released.


# Connect HiFive Unleashed and PC with USB and power it on. This interface provides UART0 (/dev/ttyUSB1) and JTAG interfaces by FTDI FT2232H ([https://www.ftdichip.com/Products/ICs/FT2232H.html link]).
== Repository ==
# Run (see simple config below and do not forget to add user to the plugdev group): <source lang=shell>$ openocd -s <path to the directory with hifive-u.cfg> -f hifive-u.cfg</source>OpenOCD will listen port 3333 for GDB connection.
# Run GDB compiled with riscv64 target support.
# Attach GDB to the OpenOCD: <source lang=shell>gdb$ target extended-remote localhost:3333</source>
# Now one could set breakpoints, investigate memory, disassemble memory regions, etc. It is possible to load an ELF file with debug information to import symbols and place breakpoints to symbols.


Example of the simple hifive-u.cfg:
RPM/SRPM repository is located at http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/


<source lang="shell>
As apt-rpm <tt>sources.list</tt>:
adapter_khz 1000


interface ftdi
rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 classic
ftdi_device_desc "Dual RS232-HS"
# rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 debuginfo
ftdi_vid_pid 0x0403 0x6010
rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/noarch  classic
ftdi_layout_init 0x0018 0x001b
ftdi_layout_signal nSRST -oe 0x0020
ftdi_layout_signal LED -data 0x0020


set _CHIPNAME riscv
Yandex mirror (better download speeds):
jtag newtap $_CHIPNAME cpu -irlen 5


set _TARGETNAME $_CHIPNAME.cpu
rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 classic
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
# rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 debuginfo
target create $_TARGETNAME.1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/noarch  classic
target create $_TARGETNAME.2 riscv -chain-position $_CHIPNAME.cpu -coreid 2
target create $_TARGETNAME.3 riscv -chain-position $_CHIPNAME.cpu -coreid 3
target create $_TARGETNAME.4 riscv -chain-position $_CHIPNAME.cpu -coreid 4
target smp $_TARGETNAME.0 $_TARGETNAME.1 $_TARGETNAME.2 $_TARGETNAME.3 $_TARGETNAME.4
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1


flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000
The information on the available packages is available here: https://packages.altlinux.org/en/sisyphus_riscv64/packages/


init
The packages are build on a separate [[girar]] instance, similar to [[Git.alt]]. SiFive [[HiFive Unmatched]] are used as build nodes.
if {[ info exists pulse_srst]} {
ftdi_set_signal nSRST 0
ftdi_set_signal nSRST z
sleep 1500
}
halt
flash protect 0 64 last off
echo "Ready for Remote Connections"
</source>


== '''OpenSBI''' ==
The "chasing builder" approach is used: as soon as a task is committed to the primary [[Sisyphus]] repository, special robot creates a similar task for <tt>sisyphus_riscv64</tt>. This means that there is no need to do anything special for building packages for '''riscv64''': build for Sisyphus. The tasks are approved manually. The resulting packages are available in the repository on the same day or on the next day most of the times.
=== QEMU virt ===
To the QEMU virt machine with one of the images one could proceed through the following steps:


'''Step 0.''' Install QEMU with riscv64 system support. For example, in the case of ALT x86_64: [http://sisyphus.ru/en/srpm/Sisyphus/qemu qemu-system-riscv-core].
We don't rebuild all the Sisyphus packages due to the limited need and resources. If you need some package that is available in Sisyphus but is missing in <tt>sisyphus_riscv64</tt>, please fill a bug or write to the mailing list: riscv-devel@lists.altlinux.org.


'''Step 1.a''' The OpenSBI firmware is placed inside the qcow2/qcow2c image. Let us copy it out of the image.
== Reporting issues ==


<source lang=shell>
For tracking bugs and issues we use ALT Linux Team bugzilla -- http://bugzilla.altlinux.org (see also: [[BugTracking]]).
root$ qemu-nbd -c /dev/nbd0 qemu-riscv64.qcow2c
root$ mount /dev/nbd0p1 /mnt
root$ cp -v /mnt/usr/share/opensbi/qemu/virt/firmware/fw_payload.elf .
user$ FIRM=./fw_payload.elf
</source>


'''Step 1.b''' Alternative option: [http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/noarch/RPMS.classic/ download]
* For issues in packages, choose product: Sisyphus, component: name of the package, and set "hardware" field to '''riscv64'''.
and install the last version of the OpenSBI for QEMU virt machine.
* For general image issues, choose product corresponding to the image type (e.g. Regular, or Simply Linux).
The OpenSBI firmware for QEMU virt will be at /usr/share/opensbi/qemu/virt/firmware/fw_payload.elf


For example:
'''IMPORTANT''':
* Set '''Hardware''' to '''riscv64''' (on the right at the top of the bug creation form)
* Assign the bug to Ivan Melnikov (iv at altlinux.org).


<source lang=shell>
== Useful links ==
user$ curl -O http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/noarch/RPMS.classic/opensbi-firmware-qemu-0.6-alt1.noarch.rpm
root$ rpm -i opensbi-firmware-qemu-0.6-alt1.noarch.rpm
user$ FIRM=/usr/share/opensbi/qemu/virt/firmware/fw_payload.elf
</source>
 
'''Step 2.''' Now, it is all set to run the QEMU with a qcow2/qcow2c image, just place the path to the image in QCOW variable:
 
<source lang="shell">
$ QCOW=qemu-riscv64.qcow2c
$ qemu-system-riscv64 \
          -nographic -machine virt -kernel "$FIRM" \
          -m 2G -smp cpus=4 \
          -drive file="$QCOW",id=hd0 -device virtio-blk-device,drive=hd0 \
          -netdev user,id=eth0,hostfwd=tcp::5900-:5900 -device virtio-net-device,netdev=eth0
</source>
 
'''Step 3.''' For a graphical system, the following system setup is performing through [[Regular/riscv64#VNC|VNC]]. To connect to the X11 VNC server one should enter the default
password '''<tt>alt</tt>''', it could be changed to another one at the inital setup of the system through GUI.
 
=== HiFive Unleashed ===
To run the SiFive HiFive Unleashed (FU540) SoC with one of the rootfs images one could proceed through the following steps:
 
'''Step 0.''' Through this manual it is assumed that microSD card is at /dev/sdb. Let us create file systems at the microSD:
 
<source lang="shell">
root$ sgdisk -g --clear \
        --new=2::+32K    --change-name=2:'fsbl'          --typecode=2:5B193300-FC78-40CD-8002-E86C45580B47 \
        --new=3::+8M:    --change-name=3:'opensbi-uboot' --typecode=3:2E54B353-1271-4842-806F-E436D6AF6985 \
        --new=1::-0      --change-name=1:'root'          --typecode=1:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \
        /dev/sdb
root$ mkfs.ext4 /dev/sdb1
root$ mount /dev/sdb1 /mnt
root$ tar -xpvf hifive-unleashed-riscv64.tar.xz -C /mnt
</source>
 
'''Step 1.а.''' The First Stage BootLoader (FSBL) and OpenSBI are placed inside the unpacked /mnt tree.
Let us write them to the 2 and 3 partitions respectively, and then unmount /mnt partition.
 
<source lang="shell">
root$ dd if=/mnt/usr/share/fu540_boot/fsbl.bin of=/dev/sdb2 bs=1M
root$ dd if=/mnt/usr/share/opensbi/sifive/fu540/firmware/fw_payload.bin of=/dev/sdb3 bs=1M
root$ sync; umount /mnt
</source>
 
'''Step 1.б.''' Alternative option: [http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/noarch/RPMS.classic/ download]
and install the First Stage BootLoader (FSBL) and OpenSBI for FU540.
 
For example:
 
<source lang="shell">
root$ curl -O http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/noarch/RPMS.classic/fu540-bootloaders-0-alt1.git54bfc90.noarch.rpm
root$ curl -O http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/noarch/RPMS.classic/opensbi-firmware-fu540-0.6-alt1.noarch.rpm
root$ rpm -i fu540-bootloaders-0-alt1.git54bfc90.noarch.rpm
root$ rpm -i opensbi-firmware-fu540-0.6-alt1.noarch.rpm
root$ dd if=/usr/share/fu540_boot/fsbl.bin of=/dev/sdb2 bs=1M
root$ dd if=/usr/share/opensbi/sifive/fu540/firmware/fw_payload.bin of=/dev/sdb3 bs=1M
root$ sync; umount /mnt
</source>
 
'''Step 3.''' System at microSD is ready to boot. For a graphical system, the following system setup is performing through [[Regular/riscv64#VNC|VNC]].
To connect to the X11 VNC server one should enter the default
 
== '''Useful links''' ==


* [[Ports/riscv64/OpenOCD]]
* [http://0x1.tv/20180929H OSSDEVCONF-2018 (in Russian)]
* [https://github.com/dalegr/riscv-bbl-utils Berkeley bootloader utils] to merge the linux kernel into the bbl.bin with dummy payload.
* [https://github.com/dalegr/riscv-bbl-utils Berkeley bootloader utils] to merge the linux kernel into the bbl.bin with dummy payload.
* [https://riscv.org/specifications RISC-V specifications]
* [https://riscv.org/specifications RISC-V specifications]
* [https://www.sifive.com/blog/all-aboard-part-0-introduction All Aboard] -- cool series of blog posts by Palmer Dabbelt about RISC-V, toolchain, etc.
* [https://www.sifive.com/blog/all-aboard-part-0-introduction All Aboard] -- cool series of blog posts by Palmer Dabbelt about RISC-V, toolchain, etc.
* [http://0x1.tv/20180929H OSSDEVCONF-2018 (in Russian)]


[[Category:Sisyphus]]
[[Category:Sisyphus]][[Category:Ports]][[Category:RISC-V]]
[[ru:Ports/riscv64]]
[[ru:Ports/riscv64]]
{{Category navigation|title=Ports|category=Ports|sortkey=*}}

Latest revision as of 12:41, 18 November 2022

Overview

Sisyphus port for riscv64 (RV64GC) architecture is under development since early 2018. The following platforms are supported:

RISC-V

RISC-V is an open and free instruction set architecture (ISA). The RISC-V ISA specifications are licensed under a Creative Commons license (CC BY 4.0). Anyone could get the final versions of the ISA specifications and participate in their development.

Another key feature of the RISC-V architecture that it is scalable and allows multiple implementations. The minimal specification has commands to store, load, jump and integer arithmetic. It supports the 32-, 64- and 128-bit register sizes: "RV32I, RV64I and RV128I" ("I" stands for integer). Implementations can provide additional functionality by extending the basic ISA -- that is, implementing standard or vendor-specific extensions.

This Linux port runs on "RV64IMAFDC"[1] architecture, which means RV64I with the following standard extensions:

  • M - Multiply and divide;
  • A - Atomic operations;
  • F - Single precision floating point;
  • D - Double precision floating point;
  • C - Compressed instructions.

For convenience, this architecture is abbreviated as "RV64GC" ("G" == "IMAFD").

Images

We build Regular Images (see also: Regular) for the supported boards and QEMU. Check out Regular/riscv64 for download links and the platform page for the quick start/installation instructions.

Also, for Unmatched/Unleashed and QEMU, Simply Linux 10 was released.

Repository

RPM/SRPM repository is located at http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64/Sisyphus/

As apt-rpm sources.list:

rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 classic
# rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/riscv64 debuginfo 
rpm [sisyphus-riscv64] http://ftp.altlinux.org/pub/distributions/ALTLinux/ports/riscv64 Sisyphus/noarch  classic

Yandex mirror (better download speeds):

rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 classic 
# rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/riscv64 debuginfo
rpm [sisyphus-riscv64] http://mirror.yandex.ru/altlinux/ports/riscv64 Sisyphus/noarch  classic

The information on the available packages is available here: https://packages.altlinux.org/en/sisyphus_riscv64/packages/

The packages are build on a separate girar instance, similar to Git.alt. SiFive HiFive Unmatched are used as build nodes.

The "chasing builder" approach is used: as soon as a task is committed to the primary Sisyphus repository, special robot creates a similar task for sisyphus_riscv64. This means that there is no need to do anything special for building packages for riscv64: build for Sisyphus. The tasks are approved manually. The resulting packages are available in the repository on the same day or on the next day most of the times.

We don't rebuild all the Sisyphus packages due to the limited need and resources. If you need some package that is available in Sisyphus but is missing in sisyphus_riscv64, please fill a bug or write to the mailing list: riscv-devel@lists.altlinux.org.

Reporting issues

For tracking bugs and issues we use ALT Linux Team bugzilla -- http://bugzilla.altlinux.org (see also: BugTracking).

  • For issues in packages, choose product: Sisyphus, component: name of the package, and set "hardware" field to riscv64.
  • For general image issues, choose product corresponding to the image type (e.g. Regular, or Simply Linux).

IMPORTANT:

  • Set Hardware to riscv64 (on the right at the top of the bug creation form)
  • Assign the bug to Ivan Melnikov (iv at altlinux.org).

Useful links

  1. In 2019, RISC-V ISA specification extracted two new extensions, Zifencei and Zicsr, from the mandatory base instruction set, and added them to 'G' set. But I'd like to constrain myself from elaborating on this in what should be a short introductory section.