Ports/riscv64

RISC-V

RISC-V is an open and free instruction set architecture (ISA). The RISC-V ISA specifications are licensed under a Creative Commons license (CC BY 4.0). Anyone could get the final versions of the user-level ISA specifications and drafts of the compressed and privileged ISA specifications.

Another key feature of the RISC-V architecture that it is scalable and allows multiple implementations. The minimal specification has the commands to store and load, jump and integer arithmetic. It supports the 32-, 64- and 128-bit register sizes: "RV32I, RV64I and RV128I" ("I" stands for integer). This Linux port runs on "RV64IMAFDC" or "RV64GC" ("G" == "IMAFD"):

• I - Integer and basic instructions
• M - Multiply and divide
• A - Atomic operations
• F - Single precision floating point
• D - Double precision floating point
• C - Compressed instructions

At this page one could find the latest information about ALT port status for the new platform - RISC-V (RV64GC). We're building it on the HiFive Unleashed board from SiFive. If you want to test the ALT port (QEMU or HiFive Unleashed) or take part in the development please refer to this page.

Working plan

• The following Linux kernels have been bare metal tested on SiFive HiFive Unleashed:
  • 4.15
  • 4.19-rc2
  • 4.19.6 (git)
  • 5.0.19 (image RPM,SRPM, git)
  • (experimetnal) 5.1.9 (image RPM, SRPM, git)

• BOOT methods:
  • Berkeley bootloader -- DONE
  • U-BOOT (link) -- DONE

• Sisyphus port -- IN PROGRESS
  1. Toolchain -- DONE
  2. Linux Kernel -- DONE
  3. X11 -- DONE
  4. Desktop Environments -- IN PROGRESS
• ALT image (link) -- DONE
• Girar Builder -- DONE
• QEMU image (see below) -- DONE

The RPM/SRPM repository at here.

OpenOCD

The OpenOCD (docs) is a tool for debugging, in-system programming and boundary-scan testing for embedded target devices. It is particularly useful for low-level debugging with (GDB) of the bootloader, Linux kernel, etc.

To debug HiFive Unleashed with OpenOCD the following steps are needed:

1. Connect HiFive Unleashed and PC with USB and power it on. This interface provides UART0 (/dev/ttyUSB1) and JTAG interfaces by FTDI FT2232H (link).
2. Run (see simple config below and do not forget to add user to the plugdev group):

   $ openocd -s <path to the directory with hifive-u.cfg> -f hifive-u.cfg
   

   OpenOCD will listen port 3333 for GDB connection.
3. Run GDB compiled with riscv64 target support.
4. Attach GDB to the OpenOCD:

   gdb$ target extended-remote localhost:3333
   

5. Now one could set breakpoints, investigate memory, disassemble memory regions, etc. It is possible to load an ELF file with debug information to import symbols and place breakpoints to symbols.

Example of the simple hifive-u.cfg:

adapter_khz 1000

interface ftdi
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010

ftdi_channel 0
ftdi_layout_init 0x0018 0x001b

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1

init
halt
echo "Ready for Remote Connections"

Useful links

• Berkeley bootloader utils to merge the linux kernel into the bbl.bin with dummy payload.
• RISC-V specifications
• All Aboard -- cool series of blog posts by Palmer Dabbelt about RISC-V, toolchain, etc.
• OSSDEVCONF-2018 (in Russian)